A novel simulation and verification approach in an ASIC design process
نویسندگان
چکیده
For the Pre-Processor System of the ATLAS Level-1 Calorimeter Trigger we have built a fast signal-processing and readout ASIC (PPrAsic). The novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Verilog HDL (hardware description language) and embedded in a system wide analog and digital simulation of implemented algorithms. We present here results of our design experience and first performance test of the Pre-Processor ASIC. Summary: Summary of a contribution to the 2000 IEEE Nuclear Science Symposium: A novel simulation and verification approach in an ASIC design process D. Husmann, M. Keller, K. Mahboubi, U. Pfeiffer, C. Schumacher Kirchhoff-Institut für Physik, Universität Heidelberg, Germany Abstract For the Pre-Processor System of the ATLAS Level-1 Calorimeter Trigger we have built a fast signal-processing and readout ASIC (PPrAsic). The novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Veriog HDL (hardware description language) and embedded in a system wide analog and digital simulation of implemented algorithms. We present here results of our design experience and first performance tests of the Pre-Processor ASIC.
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